The invention relates to semiconductor integrated circuits that have a circuit for use in self-testing and self-fault-restoring.
There have been strong demands for low-power semiconductor integrated circuits for achieving reductions in the dimensions of semiconductor devices for improving the level of integration of semiconductor devices. The reduction of power supply voltage is an effective way of implementing semiconductor integrated circuits with low power consumption. The problem is that reductions in power supply voltage result in slow transistors. A solution to this problem has been proposed. An MT-CMOS integrated circuit, as one of semiconductor integrated circuits formed by CMOS integrated circuits, has been known in the art. In the MT-CMOS integrated circuit, two types of MOS transistors are employed, namely MOS transistors having a low threshold voltage (Vth), called low-threshold MOS transistors and MOS transistors having a high Vth, called high-threshold MOS transistors.
An MT-CMOS integrated circuit is reported in TECHNICAL REPORT OF IEICE, ICD93-107 (1993-10) of THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS, which is described with reference to FIG. 1.
FIG. 1 is a circuit diagram which outlines a part of an MT-CMOS integrated circuit. Referring to FIG. 13, logic gate 99, in which many low-threshold transistors (LVth-Tr's) are placed, is connected between power supply terminal 100 at which the operation voltage (VDD) is provided and grounding terminal 101 at which the grounding potential (VGN) is provided. Connected between power supply terminal 100 and logic gate 99 is a p-channel, high-threshold transistor (pHVth-Tr 91). Further, connected between logic gate 99 and grounding terminal 101 is an n-channel, high-threshold transistor (nHVth-Tr 92). Transistors 93-96, contained in logic gate 99, are low-threshold transistors, therefore having the ability to operate at high speed and perform arithmetic operations at high speed, but on the other hand, a large leakage current will flow therein. This may lead to an increase in power consumption. To cope with this problem, HVth-Tr 91 is placed between logic gate 99 and terminal 100 and HVth-Tr 92 is placed between logic gate 99 and terminal 101.
The operation of the MT-CMOS integrated circuit of FIG. 1 is described. The electric potential of node 97 between logic gate 99 and pHVth-Tr 91 is the virtual power supply potential (VDDV), while the electric potential of node 98 between logic gate 99 and nHVth-Tr 92 is the virtual grounding potential (VGNV). Electric charges are applied to node 97 that acts as a virtual power supply terminal and to node 98 that acts as a virtual grounding terminal by having HVth-Tr 91 and HVth-Tr 92 placed in the ON state during the operation period of logic gate 99, whereby logic gate 99 formed of LVth-Tr's 93-96 starts operating at high speed. On the other hand, the supply of voltage from terminal 100 to logic gate 99 is cut off by having HVth-Tr 91 placed in the OFF state during the standby period, and HVth-Tr 92 turns off thereby suppressing leakage current from logic gate 99 to terminal 101 during the standby period. As a result, leakage from terminal 100 to terminal 101 can be held considerably low.
In a CMOS integrated circuit constructed of a PMOS circuit and an NMOS circuit, only one of them is placed in the ON state when the CMOS integrated circuit is in operation, and therefore the dissipation of power is low. When faults and/or defects, such as bridging between wires, occur in CMOS integrated circuits, power consumption is increased on the order of a few digits. This is utilized in methods, such as standby current testing and IDDQ testing, for detecting faults by observing increases in the value of electric current at the time of testing LSIs formed of CMOS integrated circuits.
As previously mentioned, with the reduction in LSI supply voltage with a view to reducing power consumption as low as possible, the reduction of Vth for MOS transistors disposed in CMOS integrated circuits has been strongly demanded in order to secure a satisfactory operating speed. However, for the case of MOS transistors low in Vth, there occurs an increase in leakage current in the standby state. To cope with such a problem, two techniques have been developed for the reduction of power consumption during the standby period. One technique employs a configuration for CMOS integrated circuits for increasing the Vth of respective MOS transistors in the standby state by substrate voltage control, i.e., a so-called variable threshold-voltage CMOS integrated circuits (VT-CMOSs) configuration. On the other hand, the other technique employs the foregoing MT-CMOS integrated circuit configuration for CMOS integrated circuits, in other words a CMOS integrated circuit configuration is provided in which a circuit of low-Vth MOS transistors is placed in the OFF state during the standby period using high-Vth MOS transistors. The MT-CMOS integrated circuit configuration has the advantage over the VT-CMOS integrated circuit configuration in that it can achieve faster switching from operation mode to standby mode.
The above-described MT-CMOS integrated circuit configuration however has the problem that the amount of leakage current occurring in standby mode increases due to each of low-Vth MOS transistors forming a CMOS integrated circuit. The proportion of an incremental amount of abnormal current accompanied with abnormal conditions (faults and/or defects) is therefore reduced, which makes it difficult to detect faults at test time. Testing including IDDQ testing is difficult to carry out.